An-Najah Blogs : Luai Malhis

Monday, January 1, 2007
A Systematic Approach for Building Processors in a Computer Design Lab Course at Universities in Developing Countries
Published at:Information Technology Journal 6 (4): 497-508, 2007
This paper presents a systematic technique for building processors by using off-the-shelf components. The main objective of this methodology is to introduce computer engineering, electrical engineering, and computer science students, in developing countries, to all phases of CPU design using very primitive ICs and home made tool kits. Using this technique, students enrolled in processor design lab can design and build processors for a defined instruction with readily available components set at minimal cost. The proposed methodology has been implemented in the computer engineering department at An-Najah National University and has proven to be efficient in teaching computer architecture and processor design, as well as boosting computer-engineering students’ self-confidence without requiring them to use very advanced laboratory equipment. Nevertheless, the sole purpose of this technique and the objective of building this microprocessor is pure educational and is not to introduce a new methodology for bu
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Wednesday, December 6, 2006
An Educational Processor: A Design Approach
Published at:An-najah university journal for research-A
In this paper, we present an educational processor developed at An-Najah National University. This processor has been designed to be a powerful supplement for computer architecture and organization courses offered at the university. The project is intended to develop an easily applicable methodology by which students get a valuable experience in designing and implementing complete processor with simple readily available off-the-shelf components. The proposed methodology is beneficial to computer engineering students enrolled at universities, specially in developing countries, where advanced laboratory equipments are rarely available. The design philosophy is to build a general-purpose processor using simple and wide spread integrated circuits. This methodology includes: defining an instruction set, datapath layout, ALU implementation, memory interface, controller design and implementation. For testing and evaluation purposes, a debugging tool is also built and implemented to serially connect the process
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Monday, February 12, 1996
An Efficient Two-Stage Iterative Method for the Steady-State Analysis of Markov Regenerative Stochastic Petri Net Models
Published at:Performance Evaluation, Volume 27-28 , (October 1996), Pages: 583 - 601
To enhance the modeling power of stochastic Petri nets SPNs, new steady-state analysis methods have been proposed for nets that include non-exponential transitions. Theunderlying stochastic process is a Markov regenerative process MRP when at most one non-exponential transition is enabled in each marking. Time-efficient algorithms for constructing and solving the MRP have been developed. However, the space required to solve such models is often extremely large. This largeness is due to the large number of transitions in the MRP. Traditional analysis methods require that all these transitions be stored in primary memory for efficient computation. If the size of available memory is smaller than that needed to store these transitions, a time-efficient computation is impossible using these methods. To use this class of SPNs to model realistic systems, the space complexity of MRP analysis algorithms must be reduced. In this paper, we propose a new steady-state analysis method that is both time and space effi
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Monday, January 1, 1996
Numerical performability evaluation of a group multicast protocol
Published at:Distrib. Syst. Engng 3 (1996) 39–52.
Multicast protocols that provide message ordering and delivery guarantees are becoming increasingly important in distributed system design. However, despite the large number of such protocols, little analytical work has been done concerning their performance, especially in the presence of message loss. This paper illustrates a method for determining the performability of group multicast protocols using stochastic activity networks, a stochastic extension to Petri nets, and reduced base model construction. In particular, we study the performability of one such protocol, called Psync, under a wide variety of workload and message loss probabilities. The specific focus is on measuring two quantities, the stabilization time—that is, the time required for messages to arrive at all hosts—and channel utilization. The analysis shows that Psync works well when message transmissions are frequent, but it exhibits extremely long message stabilization times when transmissions are infrequent and message losses o
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Monday, October 16, 1995
Numerical evaluation of a group-oriented multicast protocol using stochastic activity networks
Published at:Sixth International Workshop on Petri Nets and Performance Models (PNPM '95), 1995
Group-oriented multicast protocols that provide message ordering and delivery guarantees are becoming increasingly important in distributed system design. However, despite the large number of such protocols, little analytical work has been done concerning their performance, especially in the presence of message loss. This paper illustrates a method for determining the performability of group-oriented multicast protocols using stochastic activity networks, a stochastic extension to Petri nets, and reduced base model construction. In particular, we study the performability of one such protocol, called Psync, undera wide variety of workload and message loss probabilities. The specic focus is on measuring two quantities, the stabilization time|that is, the time required for messages to ar rive at all hosts|and channel utilization. The analysis shows that Psync works well when message transmissions are frequent, but exhibits extremely long message stabilization times when transmissions are infrequent and message l
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